The invention relates to a semiconductor design technology, and more particularly to an internal refresh signal generator for generating an internal refresh signal to conduct a refresh operation with an interval controlled based on PVT fluctuations (Process, Voltage, and Temperature).
Generally, in order that DRAM maintains information in the volatile memory cell, it periodically generates internal refresh signals for the self-refresh operation in a standby state.
When the DRAM is in an operation mode, a refresh should be performed with the external command. Also, when the DRAM is in a standby mode, a self-refresh, in which an internal refresh command is issued itself, should be performed without an external command. Moreover, the refresh operation has to be performed within a retention time which is required to maintain the information stored in the DRAM memory cell.
Typically, the self-refresh command is issued by counting a basic periodic signal (oscillation pulse), which is generated by a basic periodic signal generator, based on division signals. In order to perform the self-refresh operation in the conventional technology, a self-refresh command signal generator is provided within the DRAM and the self-refresh operation is periodically executed by a command form the self-refresh command signal generator.
FIG. 1 is a block diagram illustrating a conventional internal refresh signal generator in a semiconductor memory device. The conventional internal refresh signal generator includes a periodic signal generating unit 10 which receives a driving power and outputs both a basic periodic signal B_OSC and a half periodic signal D_OSC which has a half period of time in comparison with the basic periodic signal B_OSC, a mode selection unit 20 which selects one from the basic periodic signal B_OSC or the half periodic signal D_OSC in response to a period selecting signal DSRF_ON in order to output an unit periodic signal S_OSC, and a refresh signal generating unit 30 which produces the internal refresh signal SRF when divided signals of the unit periodic signal S_OSC are activated for a predetermined time.
The conventional internal refresh signal generator further includes a fuse selection unit 40 which supplies a cycle changing fuse signal OSC_FUSE<0:I> to change a period of the basic periodic signal B_OSC from the periodic signal generating unit 10 and a counting-number adjusting fuse signal SRF_FUSE<0:I> to control a counting number of the unit periodic signal S_OSC in the refresh signal generating unit 30. The period selecting signal DSRF_ON is a value set in the EMRS (Extended Mode Register Set). Moreover, data stored in the semiconductor memory are refreshed by the internal refresh signal SRF. Also, the periodic signal generating unit 10 includes an oscillator and the fuse selecting unit 40 can be implemented by a metal switch, instead of a fuse option.
The operation of the internal refresh generator illustrated in FIG. 1 will be described briefly. First, when the DRAM is in a standby mode, the periodic signal generating unit 10 produces the basic periodic signal B_OSC having a predetermined period and the half periodic signal D_OSC. The half periodic signal D_OSC is correspondent to a signal having a half period of the basic periodic signal B_OSC. The mode selection unit 20 selects one from the basic periodic signal B_OSC and the half periodic signal D_OSC in response to the period selecting signal DSRF_ON. The refresh signal generating unit 40 receives the unit periodic signal S_OSC, divides it, counts the divided signals, and outputs the internal refresh signal SRF in a type of a pulse signal when the counting operation is conducted over a predetermined number.
That is, as to the unit periodic signal S_OSC, the conventional internal refresh signal generator outputs a signal which is selected from the basic periodic signal B_OSC and the half periodic signal D_OSC based on the set value in the EMRS. The internal refresh signal SRF is produced by counting the unit periodic signal S_OSC based on the predetermined division. Therefore, the internal refresh signal SRF is periodically produced. Moreover, the period of the basic periodic signal B_OSC or the half periodic signal D_OSC can be adjusted by the fuse selecting unit 40 in compliance with the PVT fluctuations and the division of the unit periodic signal S_OSC can be also adjusted in the refresh signal generating unit 30.
For example, in the case where the temperature rises, the data storage time (Retention Time) of the memory cell of DRAM is decreased. Therefore, in order to prevent the data from being lost, a refresh has to be more frequently done in comparison with the common circumstance. Accordingly, in the specification prescribed in the DRAM, the EMRS sets a refresh interval over a specific temperature in order that the refresh is conducted for a period twice as much as the common refresh at a room temperature. That is, the refresh at the high temperature is frequently performed twice as much as that at the room temperature. On the other hand, in the case of the above-described conventional self-refresh, since a mask revision has to be carried out for changing the fuse option, an additional cost and time are needed. Besides, since only two cases of the room temperature and the high temperature are considered in the self-refresh operation, an excessive refresh can be performed even though it is under the high temperature situation.
Concretely, a physical experiment, such as a change of the metal switch or a metal fuse cutting, has to be verified in order that the self-refresh is in compliance with the variation of the processes. Particularly, the metal switch has to be verified through a mask revision because the metal switch is made of lower layers of a plurality of metal layers.
Further, as to the temperature variation, the conventional self-refresh operation produces an internal refresh signal for the self-refresh driving in consideration of data storage time of the DRAM memory cell at a room temperature. However, since a half period mode is used with EMRS above the specific temperature, the retention time of the memory cell is unable to be actually reflected at the high temperature. As a result, the self-refresh operation has to be executed with an excessively short cycle in consideration of the margin. That is, since the refresh cycle adjusted by the EMRS mode cannot actually reflect the temperature within the DRAM, a failure to conduct the refresh operation is caused by using the basic periodic signal at a specific high temperature or the self-refresh operation of the excessively short cycle is caused by using the half periodic signal at a low high temperature.
Finally, as to the power source voltage, the DRAM uses internal voltages which are relatively lower than an external voltage. The reason why the low internal voltage is used is that it has an effect on a signal delay with a low supply voltage of the periodic signal generator because the cycle of the self-refresh is relatively short (a few tens of microseconds). However, it is further necessary to cope with a low level of the supply voltage because the external voltage of DRAM is continuously decreased in advance.